This invention relates to a method and apparatus for making connections to large conductor arrays and more particularly to a method and apparatus for connecting to a plurality of finely spaced conductor lines which lines are the output and input lines associated with a large electro-optical display apparatus.
Based on the technical strides made in the field of very large scale integrated circuits (VLSI), it is known that the major problem in employing any circuit design is the utilization of input and output connectors which enable the integrated circuit or the circuit board to be connected to external equipment or to other circuit components. Therefore, manufacturers have developed various connectors in an attempt to follow the strides made in the field of integrated circuit design.
An even more pertinent problem is connection schemes which provide connections between different integrated circuit modules which may be located on a common circuit board. For an example of pertinent prior art techniques, reference is made to U.S. Pat. No. 3,777,221 entitled MULTILAYER CIRCUIT PACKAGE by P. A. Tatusko et al, issued on Dec. 4, 1973. This patent shows a pair of planar plates, each of which have parallel circuit conducting lines whereby circuit connections can be made between the plates. In the structure one substrate has circuit lines on a signal plane which is connected with land areas to which integrated circuit chips are attached. The other substrate is smaller with portions cut out to expose the attached chips. Circuit tabs permit edge connection to one substrate.
U.S. Pat. No. 3,829,601 entitled INTERLAYER INTERCONNECTION TECHNIQUE, issued on Aug. 13, 1974 to D. A. Jeannotte et al shows an interconnection substrate for electrical circuits. The circuits are connected by conductive metallized patterns which are deposited between alternating layers of a dielectric medium. Diffused metallurgical bond interfaces provide mechanical and electrical connection between the conductive metallized patterns and paths.
Other patents as U.S. Pat. No. 4,482,937 entitled BOARD TO BOARD INTERCONNECTION STRUCTURE, issued on Nov. 13, 1984 to W. C. Berg. This patent shows a board to board interconnection which is installed between a first multilayer circuit board and a second multilayer circuit board. The first and second boards have corresponding arrays of plated through holes which are connected to the circuit layers. The structure uses flexible contacts to frictionally couple the boards to one another.
Essentially, other patents such as U.S. Pat. No. 4,095,866 and U.S. Pat. No. 4,288,841 show other connection schemes for high density printed circuit boards. These boards may be wired together in stacked arrangements and so on as described and discussed in the above noted patents.
As one can see from such prior art patents as well as many other references, a major problem which has been considered by integrated circuit manufacturers and users is the ability to make connections to a plurality of terminals which exist on a typical integrated circuit board. The prior art is extremely aware of this problem, and it has been indicated in many publications that certain integrated circuits, while capable of being formed, are essentially impractical due to the fact that the input and output connections cannot be made. A major problem which exists in the prior art and which has surfaced recently due to technical strides made in the display industry is the problem of making connections to conductors used in closely spaced large conductor arrays. An example of the problem is best described in referring to a co-pending application entitled ELECTROPHORETIC DISPLAY PANELS AND ASSOCIATED METHODS, filed on Nov. 13, 1984 as Ser. No. 670,571 for Frank J. DiSanto, Sr. and Denis A. Kruso, the inventors herein, and assigned to the assignee herein.
In that application, there is described an electro-optical display which employs electrophoretic dispersions for producing graphic data. As indicated, such a display possesses high resolution due to the fact that the display which is an X Y grid arrangement includes, for example, 200 lines per inch in the vertical and horizontal directions. In this manner a display having dimensions of a sheet of paper of 81/2.times.11 inches would have 2,200 horizontal rows consisting of 2,200 cathode lines and 1,700 vertical columns which consist of 1,700 grid lines. Therefore, as one can ascertain, based on a fine line pattern of 200 lines per inch, it is a considerable problem to make connections to these lines utilizing prior art techniques.
It is, of course, understood that such fine line patterns are capable of being implemented by modern day integrated circuit techniques, but in order to provide for a relatively economical and reliable display assembly, one must provide a simple and economical way of making connections to large arrays of finely spaced conductors.
As will be explained, the conductors which may be between 100 to 200 conductors per inch may have a total width of 0.005 inches with a spacing between conductors of 0.005 inches and, therefore, with a spacing between the center of conductors of 0.010 inches which essentially constitute the pitch of the pattern.
As will be further explained in the specification, it is an extremely difficult problem to make connections to such an array because of the extremely small dimensions involved and to further avoid the necessity of soldering to such fine line structures.
It is, therefore, an object of the present invention to provide a method and apparatus for making connections to closely spaced large conductor arrays.